mirror of https://github.com/UMSKT/xpmgr.git
437 lines
16 KiB
C
437 lines
16 KiB
C
/*++
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Copyright (c) 2005 Microsoft Corporation
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Module Name:
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pciprop.h
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Abstract:
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This file contains custom property definitions for a PCI root bus and a PCI
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device.
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--*/
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#ifndef _PCIPROP_
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#define _PCIPROP_
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//
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// The GUID {D817FC28-793E-4b9e-9970-469D8BE63073} is a seed for all properties
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// defined for a root bus.
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//
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#define DEFINE_PCI_ROOT_BUS_DEVPKEY(_DevPkeyName, _Pid) \
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DEFINE_DEVPROPKEY((_DevPkeyName), 0xd817fc28, 0x793e, 0x4b9e, 0x99, 0x70, 0x46, 0x9d, 0x8b, 0xe6, 0x30, 0x73, (_Pid))
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//
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// This property describes the secondary side characteristics of a root bus.
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// The values for this property field are interpreted as below:
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//
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#define DevProp_PciRootBus_SecondaryInterface_PciConventional 0
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#define DevProp_PciRootBus_SecondaryInterface_PciXMode1 1
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#define DevProp_PciRootBus_SecondaryInterface_PciXMode2 2
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#define DevProp_PciRootBus_SecondaryInterface_PciExpress 3
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DEFINE_PCI_ROOT_BUS_DEVPKEY(DEVPKEY_PciRootBus_SecondaryInterface, 1); //DEVPROP_TYPE_UINT32
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//
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// This field is valid for conventional PCI and PCI-X host bridges.
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// The values for this property field are interpreted as below:
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//
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#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_Conventional_33Mhz 0
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#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_Conventional_66Mhz 1
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#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_Mode1_66Mhz 2
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#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_Mode1_100Mhz 3
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#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_Mode1_133Mhz 4
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#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_Mode1_ECC_66Mhz 5
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#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_Mode1_ECC_100Mhz 6
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#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_Mode1_ECC_133Mhz 7
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#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_266_Mode2_66Mhz 8
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#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_266_Mode2_100Mhz 9
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#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_266_Mode2_133Mhz 10
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#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_533_Mode2_66Mhz 11
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#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_533_Mode2_100Mhz 12
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#define DevProp_PciRootBus_CurrentSpeedAndMode_Pci_X_533_Mode2_133Mhz 13
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DEFINE_PCI_ROOT_BUS_DEVPKEY(DEVPKEY_PciRootBus_CurrentSpeedAndMode, 2); //DEVPROP_TYPE_UINT32
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//
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// This field is valid for conventional PCI and PCI-X host bridges.
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// The values for this property field are interpreted as below:
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//
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#define DevProp_PciRootBus_SupportedSpeedsAndModes_Pci_Conventional_33Mhz 1
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#define DevProp_PciRootBus_SupportedSpeedsAndModes_Pci_Conventional_66Mhz 2
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#define DevProp_PciRootBus_SupportedSpeedsAndModes_Pci_X_66Mhz 4
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#define DevProp_PciRootBus_SupportedSpeedsAndModes_Pci_X_133Mhz 8
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#define DevProp_PciRootBus_SupportedSpeedsAndModes_Pci_X_266Mhz 16
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#define DevProp_PciRootBus_SupportedSpeedsAndModes_Pci_X_533Mhz 32
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DEFINE_PCI_ROOT_BUS_DEVPKEY(DEVPKEY_PciRootBus_SupportedSpeedsAndModes, 3); //DEVPROP_TYPE_UINT32
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//
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// This is boolean indicating if the host bridge is capable of forwarding
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// Device ID Message transactions.
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//
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DEFINE_PCI_ROOT_BUS_DEVPKEY(DEVPKEY_PciRootBus_DeviceIDMessagingCapable, 4); // DEVPROP_TYPE_BOOLEAN
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//
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// Provides the width of a root bus interface.
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//
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#define DevProp_PciRootBus_BusWidth_32Bits 0
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#define DevProp_PciRootBus_BusWidth_64Bits 1
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DEFINE_PCI_ROOT_BUS_DEVPKEY(DEVPKEY_PciRootBus_SecondaryBusWidth, 5); //DEVPROP_TYPE_UINT32
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//
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// This is a boolean indicating that an extended config space is available
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// on the secondary side of the root bus.
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//
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DEFINE_PCI_ROOT_BUS_DEVPKEY(DEVPKEY_PciRootBus_ExtendedConfigAvailable, 6); // DEVPROP_TYPE_BOOLEAN
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//
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// This is a boolean indicating an operating system support for an extended
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// PCI config op region.
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//
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DEFINE_PCI_ROOT_BUS_DEVPKEY(DEVPKEY_PciRootBus_ExtendedPCIConfigOpRegionSupport, 7); // DEVPROP_TYPE_BOOLEAN
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//
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// This is a boolean indicating an operating system support for ASPM.
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//
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DEFINE_PCI_ROOT_BUS_DEVPKEY(DEVPKEY_PciRootBus_ASPMSupport, 8); // DEVPROP_TYPE_BOOLEAN
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//
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// This is a boolean indicating an operating system support for clock power
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// management.
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//
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DEFINE_PCI_ROOT_BUS_DEVPKEY(DEVPKEY_PciRootBus_ClockPowerManagementSupport, 9); // DEVPROP_TYPE_BOOLEAN
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//
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// This is a boolean indicating an operating system support for PCI Segments.
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//
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DEFINE_PCI_ROOT_BUS_DEVPKEY(DEVPKEY_PciRootBus_PCISegmentGroupsSupport, 10); // DEVPROP_TYPE_BOOLEAN
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//
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// This is a boolean indicating an operating system support for Message
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// Signaled Interrupts.
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//
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DEFINE_PCI_ROOT_BUS_DEVPKEY(DEVPKEY_PciRootBus_MSISupport, 11); // DEVPROP_TYPE_BOOLEAN
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//
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// This is a boolean indicating that the firmware has granted control of native
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// hot plug interrupts to the operating system.
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//
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DEFINE_PCI_ROOT_BUS_DEVPKEY(DEVPKEY_PciRootBus_PCIExpressNativeHotPlugControl, 12); // DEVPROP_TYPE_BOOLEAN
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//
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// This is a boolean indicating that the firmware has granted control of native
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// SHPC to the operating system.
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//
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DEFINE_PCI_ROOT_BUS_DEVPKEY(DEVPKEY_PciRootBus_SHPCNativeHotPlugControl, 13); // DEVPROP_TYPE_BOOLEAN
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//
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// This is a boolean indicating that the firmware has granted control over
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// native PME interrupts to the operating system.
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//
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DEFINE_PCI_ROOT_BUS_DEVPKEY(DEVPKEY_PciRootBus_PCIExpressNativePMEControl, 14); // DEVPROP_TYPE_BOOLEAN
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//
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// This is a boolean indicating that the firmware has granted control over
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// AER to the operating system.
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//
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DEFINE_PCI_ROOT_BUS_DEVPKEY(DEVPKEY_PciRootBus_PCIExpressAERControl, 15); // DEVPROP_TYPE_BOOLEAN
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//
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// This is a boolean indicating that the firmware has granted control over the
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// PCI Express capability to the operating system.
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//
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DEFINE_PCI_ROOT_BUS_DEVPKEY(DEVPKEY_PciRootBus_PCIExpressCapabilityControl, 16); // DEVPROP_TYPE_BOOLEAN
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//
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// This is a boolean indicating that the operating system is controlling PCI
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// Express features natively. Generally this will be a reflection of the
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// individual feature controls granted by the firmware and exposed by properties
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// above, but the operating system might override the firmware. The final
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// control disposition is reflected here.
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//
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DEFINE_PCI_ROOT_BUS_DEVPKEY(DEVPKEY_PciRootBus_NativePciExpressControl, 17); // DEVPROP_TYPE_BOOLEAN
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//
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// This is a boolean indicating that the system is configured to support MSI.
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// If this is FALSE no message-signaled interrupts will be allocated to devices
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// on this system, even if the operating system supports MSI.
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//
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DEFINE_PCI_ROOT_BUS_DEVPKEY(DEVPKEY_PciRootBus_SystemMsiSupport, 18); // DEVPROP_TYPE_BOOLEAN
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//
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// The GUID {3AB22E31-8264-4b4e-9AF5-A8D2D8E33E62} is a seed for all properties
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// defined for a PCI device.
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//
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#define DEFINE_PCI_DEVICE_DEVPKEY(_DevPkeyName, _Pid) \
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DEFINE_DEVPROPKEY((_DevPkeyName), 0x3ab22e31, 0x8264, 0x4b4e, 0x9a, 0xf5, 0xa8, 0xd2, 0xd8, 0xe3, 0x3e, 0x62, (_Pid))
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//
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// This property is defined to display the type of PCI device. The possible
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// values are shown below.
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//
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#define DevProp_PciDevice_DeviceType_PciConventional 0
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#define DevProp_PciDevice_DeviceType_PciX 1
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#define DevProp_PciDevice_DeviceType_PciExpressEndpoint 2
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#define DevProp_PciDevice_DeviceType_PciExpressLegacyEndpoint 3
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#define DevProp_PciDevice_DeviceType_PciExpressRootComplexIntegratedEndpoint 4
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#define DevProp_PciDevice_DeviceType_PciExpressTreatedAsPci 5
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#define DevProp_PciDevice_BridgeType_PciConventional 6
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#define DevProp_PciDevice_BridgeType_PciX 7
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#define DevProp_PciDevice_BridgeType_PciExpressRootPort 8
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#define DevProp_PciDevice_BridgeType_PciExpressUpstreamSwitchPort 9
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#define DevProp_PciDevice_BridgeType_PciExpressDownstreamSwitchPort 10
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#define DevProp_PciDevice_BridgeType_PciExpressToPciXBridge 11
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#define DevProp_PciDevice_BridgeType_PciXToExpressBridge 12
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#define DevProp_PciDevice_BridgeType_PciExpressTreatedAsPci 13
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DEFINE_PCI_DEVICE_DEVPKEY(DEVPKEY_PciDevice_DeviceType, 1);
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//
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// This property is valid for conventional PCI or PCI-X devices.
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// For conventional PCI devices, the speed/mode is described by the following
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// fields.
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//
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#define DevProp_PciDevice_CurrentSpeedAndMode_Pci_Conventional_33MHz 0
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#define DevProp_PciDevice_CurrentSpeedAndMode_Pci_Conventional_66MHz 1
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//
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// For PCI-X devices, the speed/mode is encoded in the following fashion.
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//
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#define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode_Conventional_Pci 0x0
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#define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode1_66Mhz 0x1
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#define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode1_100Mhz 0x2
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#define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode1_133MHZ 0x3
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#define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode1_ECC_66Mhz 0x5
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#define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode1_ECC_100Mhz 0x6
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#define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode1_ECC_133Mhz 0x7
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#define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode2_266_66MHz 0x9
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#define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode2_266_100MHz 0xA
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#define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode2_266_133MHz 0xB
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#define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode2_533_66MHz 0xD
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#define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode2_533_100MHz 0xE
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#define DevProp_PciDevice_CurrentSpeedAndMode_PciX_Mode2_533_133MHz 0xF
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DEFINE_PCI_DEVICE_DEVPKEY(DEVPKEY_PciDevice_CurrentSpeedAndMode, 2);
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//
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// The BaseClass, SubClass and ProgIf fields are valid for all PCI devices.
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//
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DEFINE_PCI_DEVICE_DEVPKEY(DEVPKEY_PciDevice_BaseClass, 3);
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DEFINE_PCI_DEVICE_DEVPKEY(DEVPKEY_PciDevice_SubClass, 4);
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DEFINE_PCI_DEVICE_DEVPKEY(DEVPKEY_PciDevice_ProgIf, 5);
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//
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// This property describes the current payload size in the transaction layer
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// for a PCI Express device. The encodings for this field are described below.
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//
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#define DevProp_PciExpressDevice_PayloadOrRequestSize_128Bytes 0
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#define DevProp_PciExpressDevice_PayloadOrRequestSize_256Bytes 1
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#define DevProp_PciExpressDevice_PayloadOrRequestSize_512Bytes 2
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#define DevProp_PciExpressDevice_PayloadOrRequestSize_1024Bytes 3
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#define DevProp_PciExpressDevice_PayloadOrRequestSize_2048Bytes 4
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#define DevProp_PciExpressDevice_PayloadOrRequestSize_4096Bytes 5
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DEFINE_PCI_DEVICE_DEVPKEY(DEVPKEY_PciDevice_CurrentPayloadSize, 6);
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//
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// This property describes the maximum payload size supported by an express
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// device/function. The encodings are described above.
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//
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DEFINE_PCI_DEVICE_DEVPKEY(DEVPKEY_PciDevice_MaxPayloadSize, 7);
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//
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// This property describes the maximum read request size for an express device.
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// The encoding for this field are given above.
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//
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DEFINE_PCI_DEVICE_DEVPKEY(DEVPKEY_PciDevice_MaxReadRequestSize, 8);
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//
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// This property is applicable to an express device with an express link. It
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// describes the current link speed for the device. The encodings are defined
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// as follows.
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//
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#define DevProp_PciExpressDevice_LinkSpeed_TwoAndHalf_Gbps 1
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#define DevProp_PciExpressDevice_LinkSpeed_Five_Gbps 2
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DEFINE_PCI_DEVICE_DEVPKEY(DEVPKEY_PciDevice_CurrentLinkSpeed, 9);
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//
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// This property is applicable to an express device with an express link. It
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// describes the current link width whose encoding is as follows.
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//
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#define DevProp_PciExpressDevice_LinkWidth_By_1 1
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#define DevProp_PciExpressDevice_LinkWidth_By_2 2
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#define DevProp_PciExpressDevice_LinkWidth_By_4 4
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#define DevProp_PciExpressDevice_LinkWidth_By_8 8
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#define DevProp_PciExpressDevice_LinkWidth_By_12 12
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#define DevProp_PciExpressDevice_LinkWidth_By_16 16
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#define DevProp_PciExpressDevice_LinkWidth_By_32 32
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DEFINE_PCI_DEVICE_DEVPKEY(DEVPKEY_PciDevice_CurrentLinkWidth, 10);
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//
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// This property describes the maximum link speed of an express link for an
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// express device. The encodings for this field are:
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//
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#define DevProp_PciExpressDevice_LinkSpeed_TwoAndHalf_Gbps 1
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DEFINE_PCI_DEVICE_DEVPKEY(DEVPKEY_PciDevice_MaxLinkSpeed, 11);
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//
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// This property describes the maximum link width implemented by an express
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// link for an express devce. The encodings are same as described above.
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//
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DEFINE_PCI_DEVICE_DEVPKEY(DEVPKEY_PciDevice_MaxLinkWidth, 12);
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//
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// This property describes the specification version to which an express device
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// was built. The encodings for this field are:
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//
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#define DevProp_PciExpressDevice_Spec_Version_10 1
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#define DevProp_PciExpressDevice_Spec_Version_11 2
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DEFINE_PCI_DEVICE_DEVPKEY(DEVPKEY_PciDevice_ExpressSpecVersion, 13);
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//
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// This property describes the hardware support for interrupts on the device.
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// It is a bitmask of supported interrupt types, with the following values:
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//
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#define DevProp_PciDevice_InterruptType_LineBased 1
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#define DevProp_PciDevice_InterruptType_Msi 2
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#define DevProp_PciDevice_InterruptType_MsiX 4
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DEFINE_PCI_DEVICE_DEVPKEY(DEVPKEY_PciDevice_InterruptSupport, 14);
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//
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// This property describes the number of message interrupts a device supports
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// in hardware. This property is only valid if the device supports message
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// interrupts.
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//
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DEFINE_PCI_DEVICE_DEVPKEY(DEVPKEY_PciDevice_InterruptMessageMaximum, 15);
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//
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// This property describes the number of Base Address Registers of various types
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// supported by the device hardware. The property data is a 32 bit value
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// interpreted by the following macros:
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//
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#define DevProp_PciDevice_IoBarCount(_PropertyData) ((_PropertyData) & 0xFF)
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#define DevProp_PciDevice_NonPrefetchable_MemoryBarCount(_PropertyData) (((_PropertyData) >> 8) & 0xFF)
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#define DevProp_PciDevice_32BitPrefetchable_MemoryBarCount(_PropertyData) (((_PropertyData) >> 16) & 0xFF)
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#define DevProp_PciDevice_64BitPrefetchable_MemoryBarCount(_PropertyData) (((_PropertyData) >> 24) & 0xFF)
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DEFINE_PCI_DEVICE_DEVPKEY(DEVPKEY_PciDevice_BarTypes, 16);
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//
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// This property is a BOOLEAN indicating if AER capability is present on an
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// endpoint.
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//
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DEFINE_PCI_DEVICE_DEVPKEY(DEVPKEY_PciDevice_AERCapabilityPresent, 17);
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//
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// This property indicates if a device is configured for a firmware first
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// error handling.
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//
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DEFINE_PCI_DEVICE_DEVPKEY(DEVPKEY_PciDevice_FirmwareErrorHandling, 18);
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//
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// This property provides the uncorrectable error mask for an endpoint. This
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// field is interpreted in accordance to its definition in the PCI Express
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// Base spec.
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//
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DEFINE_PCI_DEVICE_DEVPKEY(DEVPKEY_PciDevice_Uncorrectable_Error_Mask, 19);
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//
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// This property provides the uncorrectable error severity for an endpoint.
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// This field is interpreted in accordance to its definition in the PCI Express
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// Base spec.
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//
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DEFINE_PCI_DEVICE_DEVPKEY(DEVPKEY_PciDevice_Uncorrectable_Error_Severity, 20);
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//
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// This property provides the correctable error mask for an endpoint. This
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// field is interpreted in accordance to its definition in the PCI Express
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// Base spec.
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//
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DEFINE_PCI_DEVICE_DEVPKEY(DEVPKEY_PciDevice_Correctable_Error_Mask, 21);
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//
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// This property indicates if a device is capable of ECRC generation and
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// checking. This field is interpreted in according to the advanced error
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// capabilities and control register value in the PCI Express Base spec.
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//
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DEFINE_PCI_DEVICE_DEVPKEY(DEVPKEY_PciDevice_ECRC_Errors, 22);
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//
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// This property indicates if an endpoint is enabled for reporting different
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// types of error messages. This field is interpreted in accordance to the
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// device control register value as described in the PCI Express Base spec.
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//
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DEFINE_PCI_DEVICE_DEVPKEY(DEVPKEY_PciDevice_Error_Reporting, 23);
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//
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// This property indicates if a root port is enabled for reporting different
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// types of error messages. This field is interpreted in accordance to the
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// root control register value as described in the PCI Express Base spec.
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//
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DEFINE_PCI_DEVICE_DEVPKEY(DEVPKEY_PciDevice_RootError_Reporting, 24);
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//
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// This property indicates if a device can wake up via PME while the system is
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// in S0. Some platforms do not support runtime wakeup on some device types.
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//
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DEFINE_PCI_DEVICE_DEVPKEY(DEVPKEY_PciDevice_S0WakeupSupported, 25);
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#endif
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